Online Access Free EN0-001 Exam Questions

In a hardware system that runs software providing secure systems, which of the following describes the behavior of external memory and peripherals?

• A.They cannot know whether the processor is performing a Secure or Non-secure access
• B.They can use the Secure or Non-secure status of the access to decide what response to give
• C.They are not accessible when the processor is in Non-secure state
• D.They are required to give an ERROR response when Secure code accesses Non-secure locations in memory

Which of the following statements regarding Strongly-ordered memory is architecturally FALSE?

• A.Address locations marked as Strongly-ordered memory are never held in a cache
• B.The architecture does not permit speculative data accesses to Strongly-ordered memory
• C.The number and size of accesses to Strongly-ordered memory must be the same as that specified by the program
• D.A write to Strongly-ordered memory is permitted to complete before it reaches the peripheral or memory component accessed by the write

A 32KB 4-way set associative instruction cache supports a cache line size of 64 bytes. How many bits are required to index a cache line in a way?

• A.7 bits
• B.15 bits
• C.6 bits
• D.9 bits

The following pair of functions implement a simple mutex spinlock which might be used to protect a critical code section in a multi-threaded application. The address of the lock variable is in r0.

In order to minimize power while waiting for the lock to be available. SEV and WFE instructions can be used to place the processor in a low power state while waiting for the lock to become available. At which points should these instructions be placed?

• A.WFEEQ at <A> SEV at <D>
• B.SEV at<D>
• C.WFE at<B> SEV at<C> WFENE at <B>
• D.WFENE at <A>, SEV at <C>

In a system using the Security Extensions, how does the Secure Monitor execute a switch from Secure to Non-secure state?

• A.Saves Secure register contents, loads Non-secure ones from memory, sets the NS bit in SCTLR and performs an exception return
• B.Encrypts Secure register contents, sets the NS bit in SCTLR and branches directly to Normal world code
• C.Sets the NS bit in SCTLR and performs an exception return - all registers are banked in hardware and switched automatically
• D.Saves Secure register contents, sets all registers to zero, sets the NS bit in SCTLR and branches directly to Normal world code